A Guide for On-Chip Inductor Design in a Conventional CMOS Process for RF Applications

This article gives a simple set of rules for the design of integrated inductors with a good quality factor in a standard CMOS process. This guide takes into account almost all the degrees of freedom that a designer has when creating an inductor: the number of sides, the number of metal layers, the center hole, the external radius, metal width and spacing. To verify these rules, a set of inductors for different applications were patterned and measured and quality factors (Q) between 4.6 and 6 were obtained. A 3.8 nH inductor with a Q of 6.1 was manufactured and used in the design of a VCO for a 1.8 GHz application. The design served to test the performance of the VCO and also demonstrated the applicability of the inductors. The measured device phase noise equals –87 dBc per hertz at an offset frequency of 100 kHz.